发信人: champaign (原野), 信区: ECE
标 题: Motorola公司的DSP
发信站: 紫 丁 香 (Sat Oct 30 09:51:46 1999), 转信
DSP56001:
主频: 20.5, 27, or 33 MHz
位数: 24-bit fixed point DSP
24 bit data bus, 16 bit address bus,
56 bit accumulators (2)
外设: host interface port,
serial ports (2),
general purpose I/O pins, timer.
内存: Harvard architecture.
512 words program RAM, 32 words bootstrap ROM,
512 words data RAM, 512 words data ROM on chip.
封装: PGA, CQFP or PQFP packaging.
DSP56000:
Mask-programmed version of DSP56001, same peripherals and
data memories, 3.75k words program ROM on chip.
DSP56002:
特点:--- based on new 24-bit DSP56k core
--- a superset of the DSP56001 architecture
--- with On-Chip Emulation (OnCE) debug port,
--- clock PLL and improved bus arbitration
--- four cycle double precision multiply
--- support for block floating point
--- Same memory as in DSP56001,
except for 64 words bootstrap ROM.
主频: 40MHz
外设: Host interface port
serial ports (2),
general purpose I/O pins,
programmable 24-bit timer,
non-maskable interrupt
封装: PGA and CQFP packaging.
DSP56L002:
Low-power version of the DSP56002 offering identical
performance as the DSP56002 but at 3.3V.
封装: PQFP.
DSP56004:
特点: modular DSP, same 24-bit DSP56k core as in DSP56002.
Targeted to consumer digital audio applications
外设: On-Chip Emulation (OnCE) debug port
clock PLL, serial host interface (I2C and SPI)
four general purpose I/O pins,
two stereo serial audio receivers (I2S/Sony)
three stereo serial audio transmitters (I2S/Sony)
external SRAM/DRAM memory interface with 8-bit
data bus.
主频: 40 MHz (5V supply) in 80-pin QFP package.
DSP96002:
核: IEEE format floating point DSP;
two complete 32 bit data and address buses;
Harvard architecture.
内存:1k words program RAM,
64 words bootstrap ROM,
1k words data RAM,
1k words data ROM,
主频: Available in 33 MHz or 40 MHz
封装: 223-pin PGA packaging.
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