Electronics 版 (精华区)

发信人: zjliu (秋天的萝卜), 信区: Electronics
标  题: 七段译码器vhdl程序 zz
发信站: 哈工大紫丁香 (Wed Apr 14 20:46:51 2004), 站内信件

发信站: 四川大学蓝色星空站  

library ieee;
use ieee.std_logic_1164.all;
entity sev_v is
       port (d: in  std_logic_vector(3 downto 0);
             s: out std_logic_vector(6 downto 0)
            );
end sev_v;

architecture a of sev_v is
begin
    process(d)
       begin
           case d is
                when "0000"=>  s<="0000001";
                when "0001"=>  s<="1111001";
                when "0010"=>  s<="0010010";
                when "0011"=>  s<="0000110";
                when "0100"=>  s<="1001100";
                when "0101"=>  s<="0100100";
                when "0110"=>  s<="0100000";
                when "0111"=>  s<="0001111";
                when "1000"=>  s<="0000000";
                when "1001"=>  s<="0000100";
                when others=>  s<="1111111";
           end case;
     end process;
end  a;


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※ 来源:．哈工大紫丁香 bbs.hit.edu.cn [FROM: 202.118.229.162]